Pipeline Details

Toast has a classic 5-stage pipeline with the following stages:

Instruction Fetch (IF)

Fetches instruction from memory via the Instruction Memory interface. Requires one cycle to execute. See Instruction Fetch Stage (IF) for details.

Instruction Decode (ID)

Decodes the fetched instruction, generates control signals, and fetches register file data for decoded instruction. Outputs are registered, stage requires one cycle to execute. See Instruction Decode Stage (ID) for details.

Execute (EX)

Muxes the correct operands into the ALU and performs operation based on control signals. Outputs are registered, stage requires one cycle to execute. See Execute Stage (EX) for details.

Memory Access (MEM)

All loads and stores are handled in this stage. See Memory Stage (MEM) for details.

Writeback (WB)

For now serves as a simple pass through back to the register file, containing only a single mux that controls whether memory data or the ALU result is written.

Pipeline Control

Pipeline forwarding and stalls are handled by a separate control module (rtl/toast_control). The control module is composed of combinatorial logic and checks for data hazards in the EX and MEM stages.