Toast: A 32-bit RISC-V Core

Toast is a 32-bit RISC-V core written in Verilog that implements a subset of the RV32I ISA version 2.2.

Toast supports all instructions from the RV32i base integer ISA with the exception of CSR, FENCE, EBREAK, and ECALL. Toast also does not support interrupt handling, although these features may be added in the future.

Toast has been tested using the official RV32ui unit tests from the riscv-tests repo but has not been formally verified.

Contents

• Pipeline Details
  • Pipeline Control
• Instruction Fetch Stage (IF)
  • Normal Operation:
  • Conditional Branch Taken:
  • Jump Taken:
• Instruction Decode Stage (ID)
  • Decoder:
  • Register File:
• Execute Stage (EX)
  • ALU:
  • Branch Gen:
• Memory Stage (MEM)
  • Loads:
  • Stores: